Samsung Electronics has become the world’s first company to mass produce 3 nanometer foundry chips. Global semiconductor producers have so far employed the most advanced 4 nanometer process.
As U.S. President Joe Biden and Korean President Yoon Suk-yeol toured Samsung Electronics’ plant in Pyeongtaek, Gyeonggi-do, in June, Samsung Electronics Vice Chairman Lee Jay-yong unveiled a prototype of a 3 nanometer chip.
Industry analysts said Samsung Electronics was evaluated to have secured a foothold to beat Taiwan’s TSMC, the world’s No.1 foundry maker.
Samsung Electronics announced on June 30 that it has started initial production of its 3-nanometer (nm) process node applying Gate-All-Around (GAA) transistor architecture.
Multi-Bridge-Channel FET (MBCFET), Samsung’s GAA technology implemented for the first time, defies the performance limitations of FinFET.
It improves power efficiency by reducing the supply voltage level, while also enhancing performance by increasing drive current capability.
Samsung is starting the first application of the nanosheet transistor with semiconductor chips for high performance, low power computing application and plans to expand to mobile processors.
“Samsung has grown rapidly as we continue to demonstrate leadership in applying next-generation technologies in manufacturing, such as the foundry industry’s first High-K Metal Gate, FinFET, as well as EUV. We seek to continue this leadership with the world’s first 3nm process with the MBCFET,” said Dr. Choi Si-young, President and Head of Foundry Business at Samsung Electronics.
“We will continue active innovation in competitive technology development and build processes that help expedite achieving maturity of technology.”
Samsung’s proprietary technology utilizes nanosheets with wider channels, which allow higher performance and greater energy efficiency compared to GAA technologies using nanowires with narrower channels.
Utilizing the 3nm GAA technology, Samsung will be able to adjust the channel width of the nanosheet in order to optimize power usage and performance to meet various customer needs.
In addition, the design flexibility of GAA is highly advantageous for Design Technology Co-Optimization (DTCO), which helps boost power, performance, area (PPA) benefits.
Compared to the 5nm process, the first-generation 3nm process can reduce power consumption by up to 45%, improve performance by 23% and reduce area by 16% compared to 5nm, while the second-generation 3nm process is to reduce power consumption by up to 50%, improve performance by 30% and reduce area by 35%.
Samsung Electronics Vice Chairman Lee Jay-yong talks with ways of cooperating with CEO Peter Wennink of ASML at ADML headquarters in Eindhoven, the Netherlands, on June 14.
Samsung Vice Chmn. Lee Resumes Overseas Field Business Tour for 1st Time in 6 Months
Lee Jay-yong, the de factor leader of Samsung Electronics, left for Europe via a chartered flight on June 7, resuming his oversees field business inspection tour for the first time in six months.
Vice Chairman Lee launched his global business tour as he visited the United States in November and the Middle East in December. Business sources said Lee’s tour to Europe was designed to restore the ruptured global network and explore new business opportunities, as he did last year.
They said Vice Chairman Lee toured Hungary, Germany, the Netherlands, Belgium and France.
Initially, Vice Chairman Lee visited the global leading chip equipment producer ASML headquarters in Veldhoven, Netherlands, and discussed on the supply of extreme ultra-violet lithography equipment, essential to produce next-generation chips.
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