Samsung Electronics Challenges TSMC¡¯s Dominance with ¡®AI Chip One-Stop-Shop Production¡¯
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Samsung Electronics Challenges TSMC¡¯s Dominance with ¡®AI Chip One-Stop-Shop Production¡¯
Takes up gauntlet with advanced technologies like GAA and BSPDN

30(Thu), Oct, 2025




Samsung Electronics Chmn. Lee Jae-yong shakes hands with Open AI CEO Sam Altman at Samsung Electronics Building in Seocho-dong, Seoul, after signing an LOI to build key infrastructure for global AI on Oct. 1. (Photo: Samsung Electronics)


Samsung Electronics, declaring a three-way competition with TSMC and Intel on the AI foundry market, is anticipating a major gap based on next-generation technologies, such as the Gate-All-Around (GAA) transistor architecture and the Backside Power Delivery Network (BSPDN). 

The integrated support strategy encompassing memory and packing aims to own a 15 percent share in the foundry market by 2030. 

Samsung Electronics is taking up the gauntlet based on one-stop-shop solutions to take the hegemony over the AI semiconductor market, growing at a brisk face. 

The Korean electronics giant is taking on market leaders like TSMC and Intel by capitalizing on integrated support strategies of memory, foundry and advanced packing and advanced technologies, such as GAA and BSPDN with the goal of becoming an AI hardware integrated solution provider going beyond a simple manufacturer. 

Samsung¡¯s offensive based on massive investments and technology innovation is predicted to bring about tremendous changes in the global semiconductor landscape, further intensifying technology competition in the AI era, the Financial Content reported on Oct. 4. 

Samsung Electronics¡¯ core strategy lies the establishment of an AI semiconductor integrated development and production system. 

The company targets optimized AI chip supply tailored to meet customers¡¯ needs by handling all production processes, ranging from AI chip development to production through the establishment of a design-memory-production-packing one-stop-shop ecosystem. 

The integrated approach could have an effect of reducing chip production times by 20 percent through the efficient whole production process. 

The strategy in the semiconductor sector, in which time-to-market is essential, could prove to be a strong competitive edge. 

Samsung Electronics has an ambition to open an efficient path encompassing all processes, ranging from design to final products to fabless companies, which try to realize high-performance, low-power and high bandwidth. 


GAA¡¤BSPDN, Samsung¡¯s Two Advanced Technologies 

Samsung¡¯s confidence comes from the world¡¯s first mass production of GAA transistor architecture and the innovative technology BSPDN. In 2022, Samsung Electronics proved technology leadership by introducing the GAA technology in the world¡¯s first 3-nano process. 

Samsung Electronics¡¯ strategy aims to create a three-way competition among TSMC, Intel and Samsung. 

The frontrunner in the global foundry market is TSMC, which introduced a 2-nano and a 1.6-nano process in 2025 and 2026, respectively. 

Intel, declaring its reentry in the foundry market, is making a comeback with a 18A process with advanced technologies, such as RibbonFET and PowerVia.

Amid the latest developments, Samsung Electronics has recently made a splash. 

One achievement is Samsung Electronics¡¯ $16.5 billion deal to supply the next-generation self-driving chip A16 to Tesla with a 3-nano process. 

Partnerships like a memory supply cooperation deal with Open AI and its strategic investment into Rebellions, a new fabless company in Korea, are conductive to raising its market reliability.
 

Samsung Begins Chip Production Using 3nm Process Technology with GAA Architecture

Samsung Electronics, the world leader in semiconductor technology, announced on June 30 that it started initial production of its 3-nanometer (nm) process node applying Gate-All-Around (GAA) transistor architecture.

Multi-Bridge-Channel FET (MBCFET), Samsung¡¯s GAA technology implemented for the first time ever, defies the performance limitations of FinFET, improving power efficiency by reducing the supply voltage level, while also enhancing performance by increasing drive current capability.

Samsung is starting the first application of the nanosheet transistor with semiconductor chips for high performance, low power computing application and plans to expand to mobile processors. 

¡°Samsung has grown rapidly as we continue to demonstrate leadership in applying next-generation technologies to manufacturing, such as foundry industry¡¯s first High-K Metal Gate, FinFET, as well as EUV. We seek to continue this leadership with the world¡¯s first 3nm process with the MBCFET¢â,¡± said Dr. Choi Si-young, President and Head of Foundry Business at Samsung Electronics. 

¡°We will continue active innovation in competitive technology development and build processes that help expedite achieving maturity of technology.¡± 


Design-Technology Optimization for Maximized PPA

Samsung¡¯s proprietary technology utilizes nanosheets with wider channels, which allow higher performance and greater energy efficiency compared to GAA technologies using nanowires with narrower channels. 

Utilizing the 3nm GAA technology, Samsung will be able to adjust the channel width of the nanosheet in order to optimize power usage and performance to meet various customer needs.

In addition, the design flexibility of GAA is highly advantageous for Design Technology Co-Optimization (DTCO), which helps boost Power, Performance, Area (PPA) benefits. 

Compared to the 5nm process, the first-generation 3nm process can reduce power consumption by up to 45%, improve performance by 23% and reduce area by 16% compared to 5nm, while the second-generation 3nm process is to reduce power consumption by up to 50%, improve performance by 30% and reduce area by 35%.


Providing 3nm Design Infrastructure & Services With SAFE Partners

As technology nodes get smaller and chip performance needs grow, IC designers face challenges in handling tremendous amounts of data to verify complex products with more functions and tighter scaling. 

To meet such demands, Samsung strives to provide a more stable design environment to help reduce the time required for design, verification and sign-off process, while also boosting product reliability.

Since the third quarter of 2021, Samsung Electronics has been providing proven design infrastructure through extensive preparation with Samsung Advanced Foundry Ecosystem (SAFE) partners including Ansys, Cadence, Siemens and Synopsys, to help customers perfect their product in a reduced period of time. 


   
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